module Regs(
    input clk, rst, RegWrite,
    input [4:0] ReadAddr_rs, ReadAddr_rt,
    input [4:0] WriteAddr_rd,              //需要注意的是不同指令可能名称不同
    input [31:0] WriteData,
    output [31:0] ReadData_rs, ReadData_rt 
);
reg [31:0] RegRam[31:0];
integer  i;

always@(negedge clk or negedge rst)
begin
  if(!rst) begin
      for(i=0; i<32; i=i+1)begin
      RegRam[i] <= 0;
      end
  end else if(RegWrite==1)begin
      RegRam[WriteAddr_rd] <= WriteData;
  end 
end

assign ReadData_rs = ((RegWrite==1)&(WriteAddr_rd==ReadAddr_rs))? WriteData:RegRam[ReadAddr_rs];
assign ReadData_rt = ((RegWrite==1)&(WriteAddr_rd==ReadAddr_rt))? WriteData:RegRam[ReadAddr_rt];
    
endmodule 